1. Technical Field
This invention generally relates to systems modeling and development, and more specifically relates to hardware simulators with a hardware accelerator.
2. Background Art
Today's integrated circuit (IC) systems are often a highly complex combination of hardware and software that must function within very specific constraints in order for the computer system to operate as designed. Computer aided design tools allow IC designers to model a new design and to model how the new design will interact with and respond to existing systems or components prior to production. Modeling with computer aided design tools can significantly accelerate the design process and reduce the time to market for IC systems, which can be a competitive advantage. This modeling is typically accomplished by using simulation systems that model hardware function and performance in software, hardware-accelerated software simulation systems, or hardware emulation systems that use a combination of software and hardware to model a circuit or system design.
Simulation has long been a preferred method for verification of logical correctness of complex electronic circuit designs. Simulation is broadly defined as the creation of a model which, if subjected to arbitrary stimuli, responds in a similar way to the manufactured and tested design. More specifically, the term “simulation” is typically used when such a model is implemented as a computer program. In contrast, the term “emulation” is the creation of a model using programmable (also known as reconfigurable) logic or field-programmable gate array (FPGA) devices. Simulation/Emulation saves a significant amount of time and financial resources because it enables designers to detect design errors before the expensive manufacturing process is undertaken. Moreover, the design process itself can be viewed as a sequence of steps where the initial general concept of a new product is being turned into a detailed blueprint. Detecting errors at the early stages of this process also saves time and engineering resources. The primary advantage of emulation over simulation is speed. However emulation typically lacks access to internal nodes needed for detailed analysis. Simulation acceleration uses special a purpose hardware accelerator to speed up the model evaluation. Simulation acceleration has the advantages of software simulation and increased speed.
The typical IC design process describes the IC logic in Very high speed IC Hardware Description Language (VHDL) or some other type of hardware description language, feeds VHDL into a simulation environment, and loads a netlist which describes the interconnection topology of the design into a hardware accelerator. The hardware accelerator typically is a chassis full of software programmable logic such as an array of multiplexers. Software evaluates the netlist and partitions it so that the programmable logic can be programmed to simulate the topology of the proposed design. The designer then interacts with the hardware accelerator to simulate and evaluate the operation of the proposed IC design.
Referring now to FIG. 1, a typical simulation environment 100 includes a workstation 110, and a hardware accelerator 120. A communication link 130 provides an intercommunication link between the work station and the hardware accelerator 120. In this prior art simulation system 100, the simulation model 140 in the hardware accelerator 120 has separate partitions for latches 150 and combinational logic 160. Workstation 110 may be any type of microprocessor-based computer or computer system known to those skilled in the art. Hardware accelerator 120 is a large-scale hardware configuration implemented with programmable logic such as multiplexer arrays or some other type of custom hardware. Some hardware accelerators 120 include a function unit array 170. This system is capable of using the function unit array 170 to emulate many different types of computer system hardware components including, for example, combinational logic, latches and memory devices.
FIG. 2 shows another simulation system believed to be in the prior art. This simulation environment 200 includes a workstation 110, and a hardware accelerator 120. A communication link 130 provides an intercommunication link between the work station and the hardware accelerator 120. In this prior art simulation system 200 the hardware accelerator 120 has a simulation model 140 that has a single partition 210 for latches and combinational logic. The hardware accelerator 110 includes a function unit array 170 as described above with reference to FIG. 1. This system relies on virtual logic to provide the benefits of a latch only cycle and a combinational only cycle, which decreases system performance.
In an IC design, there are memory elements such as latches and arrays, and combinatorial logic elements such as “AND” and “OR” gates. In a simple design, the output values from the latches propagate through the combinational logic. The output of the combinational logic becomes the input of the latches that are updated on the next “clock”. A simulation cycle would consist of the following sequence:latches→combinational logic - - - (clock)→latches
During simulation, developers want to look at the values of both latches and combinational logic, and the general expectation is that the values of the combinational logic correspond to the output of the latches, i.e. the state of the design before the “clock”. If developers were to only read signals, the simulator would only have to stop the simulator after the combinational logic. A simulation cycle would consist of the following sequence:
“user control (read, clock)” --> “update latches” --> “updatecombinational” --> “user control”.However, developers also have the option of changing or sticking the values of latches and signals when the simulation is continued after a user control stop. If the developer changes a latch or signal and then issues a “clock” command, the expectation is that the latches will be updated based on the changes that the user made. Therefore, in this case, a simulation cycle would consist of the following sequence:
“user control (read/alter/stick, clock)” --> “update combinational” -->“update latches” --> “update combinational” --> “user control”.In the last example, the combinational logic is evaluated twice (before and after the user control). The combinational logic is updated before the user control so that the developer would have access to the updated signal values. The update combinational after user control can be deferred and only done on user control cycles when the user actually alters signals.
In more complex designs, there can be memory elements within the combinational logic such as transparent latches. Transparent latches act like latches in that they can retain their previous cycle's value, but they act like combinational logic in that their output is updated right away, without waiting for a clock. Because of these memory elements, there may be a feedback loop within the combinational logic such that the output will be different after updating the combinational logic several times. Depending on the runtime environment, the simulator may be able to avoid ever having to update the combinational logic more than once, or this feedback behavior may be accepted/expected by the users.
In some prior art simulators like the Awan simulator developed by IBM, the model contains two separate partitions (a combinational partition followed by a latch partition). The functions of update latches and update combinational are achieved by setting the simulator's start and end address to the partition's start and end address. So to clock a large number of cycles at a time, the start and end address would be set so that both partitions are run, and the simulation would stop after evaluating the latch partition. This made it simple to avoid multiple combinational logic evaluations as described above.
In some simulators, including those that employ more parallelism to increase speed, there are no separate partitions for latches and combinational logic. Within the model, the latches are placed before the combinational logic that they feed, so that one or more full cycles would end after evaluating the combinational logic. Whenever the simulator needs to update either the latches or the combinational logic, both are actually evaluated. So the simulator cannot perform an update latches and an update combinational by running the separate models in the separate partitions for latches and combinational logic.